A data transmitting/receiving apparatus will be described with reference to the accompanying drawings. FIG. 1 is a schematic view illustrating a display having a related data transmitting/receiving apparatus. Referring to FIG. 1, a timing controller 2 may be a data transmitter, and a source driver (or a column driver) 4 may be a data receiver.
A reduced swing differential signaling (RSDS) system or a mini-low voltage differential signaling (mini-LVDS) system may be used for an interface between a timing controller and a source driver. However, the features of either the RSDS system or the mini-LVDS system, namely, the feature of converting a current into a voltage using a termination resistor at the side of a data receiver and the feature of transmitting a signal from a data transmitter to the data receiver in a multi-drop manner, incur many problems in an LCD device, which includes a panel exhibiting a high resolution while having a large area. This is because an increase in data transmission rate and an increase in the number of signal lines occur, so that the system becomes complicated. In the multi-drop mode, it is difficult to secure a desired signal transmission quality because a source driver is shared among all signal lines. Furthermore, use of a clock signal having a high frequency causes high electromagnetic interference (EMI). In order to overcome the above-mentioned problems, an advanced intra panel interface (AiPi) has been proposed. The basic concept of the AiPi interface is to adopt driving in a point-to-point mode, in place of driving in the multi-drop mode. The feature of this system is to introduce the concept of embedding a clock line in a data line, in order to reduce the number of signal lines while eliminating skew of data and signal lines.
FIG. 2 is a waveform diagram of a transmit signal explaining the concept of embedding a clock signal in data. As shown in FIG. 2, a data line is swung among multiple levels to discriminate data and a clock signal from each other. A data receiver, which receives the transmit signal shown in FIG. 2, uses reference voltages Vrefh and Vrefl, in order to discriminate data and the clock signal contained in the transmit signal. In accordance with this system, it is possible to reduce the number of signals, and to use a low operation frequency. Accordingly, there is an advantage in terms of costs. In addition, superior characteristics are exhibited in terms of EMI or signal quality, as compared to the RSDS or mini-LVDS system. However, the AiPi interface has a problem in terms of signal recovery. That is, the reference voltages Vrefh and Vrefl used to discriminate data and a clock signal from each other are generated in a source driver. Also, conversion of current to voltage is carried out using a termination resistor. For this reason, there is a problem in that, when variations in reference voltages Vrefh and Vrefl occur in a direction opposite to a variation in current in the data transmitter, namely, the timing controller, it is impossible to discriminate data and a clock signal from each other, so that it is impossible to recover a desired signal. Thus, the system, in which data and a clock signal are discriminated using the reference voltages, has a problem in that it is sensitive to variations in current and voltage.
FIG. 3 is a diagram schematically illustrating a timing controller 10 and a source driver 20. Referring to FIG. 3, a clock signal output from a clock driver 12 and data output from a data driver 14 are synthesized in a synthesizer 16. The synthesized signal is transmitted from the timing controller 10 to the source driver 20. The source driver 20 converts the synthesized signal into a voltage, using a termination resistor R1, compares the voltage with reference voltages, and separates the clock signal and data from the voltage signal in accordance with the result of the comparison.
When the resistances of signal lines between the timing controller 10 and the source driver 20 are increased in the case in which a current is converted into a voltage using the termination resistor R1, as shown in FIG. 3, it is difficult to achieve signal recovery due to voltage drop occurring across resistors RL1 and RL2 formed by the resistances of the signal lines. In particular, the AiPi interface system has a problem in that signal recovery is more difficult because the current at the transmitting stage of the timing controller 10 is higher than data, for the generation of the clock signal, in the AiPi interface system, as shown in FIG. 2.
In a panel having a size of 12.1 inches or less such as a notebook, a chip-on-glass (COG) structure is used, in place of a bonding structure using a related chip-on film (COF) or a related tape carrier package (TCP), in order to achieve an enhancement in price competitiveness. In the COG structure, a chip is bonded to a glass without using a tape. In this case, a flexible printed circuit board (FPC) is used to connect power and control signals between a control board and a driver. In order to reduce the area of the FPC, and thus to achieve an enhancement in price competitiveness, power and signal lines are also patterned the glass. However, the signal lines formed on the glass exhibit an increased resistance, as compared to a printed circuit board (PCB). For this reason, there is a difficulty in driving the LCD panel using the COG structure in currently-used interface systems such as the RSDS, mini-LVDS, and AiPi systems.